LIST ; P16F84.INC Standard Header File, Version 2.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F84 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F84 ; 2. LIST directive in the source file ; LIST P=PIC16F84 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ; 23/11/97 すべてのレジスタの名称をメーカー純正のものに変更. ; ビット名のみでアクセス可能に変更. by M.Yazawa ;2.00 07/24/96 Renamed to reflect the name change to PIC16F84. ;1.01 05/17/96 Corrected BADRAM map ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== ; IFNDEF __16F84 ; MESSAG "Processor-header file mismatch. Verify selected processor." ; ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU 0x00 TMR0 EQU 0x01 PCL EQU 0x02 STATUS EQU 0x03 FSR EQU 0x04 PORTA EQU 0x05 PORTB EQU 0x06 EEDATA EQU 0x08 ;16F84 ONLY EEADR EQU 0x09 ;16F84 ONLY ADCON0 EQU 0x08 ;16C71 ONLY ADRES EQU 0x09 ;16C71 ONLY PCLATH EQU 0x0A INTCON EQU 0x0B OPTION_REG EQU 0x01 TRISA EQU 0x05 TRISB EQU 0x06 PCON EQU 0x07 ;16C71 ONLY ADCON1 EQU 0x08 ;16C71 ONLY EECON1 EQU 0x08 EECON2 EQU 0x09 ;----- STATUS Bits -------------------------------------------------------- #DEFINE IRP STATUS,7 #DEFINE RP1 STATUS,6 #DEFINE RP0 STATUS,5 #DEFINE TO STATUS,4 #DEFINE PD STATUS,3 #DEFINE Z STATUS,2 #DEFINE DC STATUS,1 #DEFINE C STATUS,0 ;----- ADCON0 Bits -------------------------------------------------------- #DEFINE ADCS1 ADCON0,7 #DEFINE ADCS0 ADCON0,6 #DEFINE CHS1 ADCON0,4 #DEFINE CHS0 ADCON0,3 #DEFINE GO ADCON0,2 #DEFINE NOT_DONE ADCON0,2 #DEFINE GO_DONE ADCON0,2 #DEFINE ADIF ADCON0,1 #DEFINE ADON ADCON0,0 ;----- INTCON Bits -------------------------------------------------------- #DEFINE GIE INTCON,7 #DEFINE EEIE INTCON,6 #DEFINE T0IE INTCON,5 #DEFINE INTE INTCON,4 #DEFINE RBIE INTCON,3 #DEFINE T0IF INTCON,2 #DEFINE INTF INTCON,1 #DEFINE RBIF INTCON,0 ;----- OPTION Bits -------------------------------------------------------- #DEFINE RBPU OPTION_REG,7 #DEFINE INTEDG OPTION_REG,6 #DEFINE RTS OPTION_REG,5 #DEFINE RTE OPTION_REG,4 #DEFINE PSA OPTION_REG,3 #DEFINE PS2 OPTION_REG,2 #DEFINE PS1 OPTION_REG,1 #DEFINE PS0 OPTION_REG,0 ;----- PCON Bits -------------------------------------------------------- #DEFINE POR PCON,1 #DEFINE BOR PCON,0 ;----- ADCON1 Bits -------------------------------------------------------- #DEFINE PCFG1 ADCON1,1 #DEFINE PCFG0 ADCON1,0 ;----- EECON1 Bits -------------------------------------------------------- #DEFINE EEIF EECON1,4 #DEFINE WRERR EECON1,3 #DEFINE WREN EECON1,2 #DEFINE WR EECON1,1 #DEFINE RD EECON1,0 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'CF' __BADRAM H'07', H'50'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ON EQU H'000F' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST